Many electronic devices make use of at least one clock signal to synchronize the operation of various parts of the circuit and for timing/counting purposes. This signal usually has a very accurate frequency and duty cycle (that is, the frequency and duty cycle are substantially constant) and may be generated, for example, by passing the sinusoidal output of a crystal oscillator circuit through a comparator circuit to convert it to a digital signal.
Many electronic devices also make use of a clock frequency multiplier circuit to generate a higher frequency signal than the clock signal. A typical clock multiplier circuit 100, as shown in FIG. 1, may use a phase locked loop (PLL) including a phase detector 102, low pass filter 104, voltage controlled oscillator (VCO) 106 and a divide by N circuit 108. An input clock signal is provided to the phase detector 102. By keeping the output of the divide by N circuit 108 in-phase with the input 110, the output 112 from the VCO will have a frequency N*Fin, where Fin is the frequency of the input clock signal. The operation of phase locked loops can be understood from, for example, B. Razavi, “Monolithic Phase-locked loops and clock recovery circuits”, IEEE press, 1996, the contents of which are incorporated herein by reference for all purposes. The PLL-based circuit 100 has a high circuit complexity and power consumption.
A simpler clock frequency doubling circuit 200, which doubles the frequency of a clock signal (that is, produces a clock signal of twice the frequency of an input clock signal) is shown in FIG. 2. The circuit 200 includes an input clock signal 202 which is provided to a first input of a XOR gate 204. The input 202 is also provided to a delay cell 206 which delays the signal by a predetermined amount, and then provides it to a second input of the XOR gate 204. The output 208 of the XOR gate 204 comprises a clock signal with a higher frequency than the input clock signal. As shown in FIG. 3, the output 300 from the delay cell is delayed by a time T relative to the clock signal input 202. The output 208 of the XOR gate 204 comprises a clock signal where the signal is high when the signals 202 and 300 are not at the same logic level. The output 208 has a frequency which is double that of the input 202, and the pulses have a width of T. Therefore, the duty cycle is defined by the delay cell 206. In practice, the delay cell may be poorly defined, which can make a desired duty cycle (such as, for example, a duty cycle of 50%) difficult to achieve.
It is an object of embodiments of the invention to at least mitigate one or more of the problems of the prior art.